1. Field of the Invention
This invention relates to a spread-spectrum signal receiving method which is used, for example, in a communications system utilizing a direct-sequence spreadspectrum communication method (DS-CDMA) and to an apparatus thereof.
2. Description of the Prior Art
Spread-spectrum communication method is a method in which the spectrum of information signal is spread into a broad band and transmitted, by using a spreading code. The method is broadly divided into Direct Sequence (DS), Frequency Hopping (FH) and Time Hopping (TH) methods. The Direct Sequence method performs a spectrum spreading by calculating a product of pseudo-noise code and information signal. Spreading ratio of the spectrum is determined by a ratio of a spreading code rate to an information signal rate. This ratio is called a spreading rate or a processing gain (the value of a spreading rate in dB).
Communications using the spread-spectrum communication method have various advantages such as resistance to interference, a low interception rate or a low interference, resistance to a multi-path fading, ability of performing multiple access, etc. Since these advantages are particularly preferable for mobile communication, investigations have been made to adopt the spread-spectrum communication method into the mobile communication and this kind of mobile communication has been put into practical use. For connecting a mobile station and a base station, the spread-spectrum communication employs a method of discriminating these stations based on pseudo-noise codes used for the spread spectrum. This method of making a connection between the mobile station and the base station is called a Code Division Multiple Access (CDMA) method.
FIGS. 15 and 16 show arrangements of a conventional communications apparatus used in a direct-sequence spread-spectrum (DS-SS) communication which was presented by B. Y. Young et al. in IEEE Journal of Selected Areas in Communications, vol. 11, No. 7, pp. 1096-1107, entitled "Performance Analysis of An All-Digital BPSK Direct-Sequence Spread-Spectrum IF Receiver Architecture". FIG. 15 illustrates a transmission part and FIG. 16 indicates a reception part. In some cases, a signal processing part which is coherent to the spread spectrum is composed of an analog circuit. However, in light of reliability, no adjustment, hardware scale, mass-productivity (i.e. a production cost), and other requirements of the circuit, the signal processing part is in most cases realized by a digital circuit, like the traditional apparatus mentioned above.
The transmission part shown in FIG. 15 will be explained below. Data which is equivalent to information data, is input to a data spreader 1 of the transmission part. In the data spreader 1, a data encoder 2 performs data encoding such as a voice encoding, error-correction encoding, framing processing, etc., then outputs encoded data as a symbol. A spreader 3 makes a product of this encoded data and pseudo-noise codes given by a pseudo-noise code generator (PN Generator) 4. The product becomes a data spreader output which is then input to a modulator 5. In the modulator 5, a multiplier 7 multiplies this input and a carrier-wave signal provided by a local oscillator (RF OSC) 6, so as to perform carrier modulation. Output from the multiplier 7 is amplified in power by an amplifier (AMP) 9 after its modulated component is extracted by a band-pass filter (BPF) 8. Then, the amplified signal is transmitted from an antenna 10 as a high-frequency output signal (RF Output).
It should be noted that encoded data is hereinafter referred to as "a symbol", so as to distinguish data coded by a coding device 2 from the information data. The symbol takes a form of bi-phase digital phase shift keying (BPSK), quadrature digital phase shift keying (QPSK), quadrature amplitude modulation (QAM) or the like, in accordance with a carrier modulation method.
The reception part shown in FIG. 16 will be explained below. Antenna 11 receives a high-frequency signal which will become a high-frequency input (RF Input), and a band-pass filter (BPF) 12 extracts a received signal component from the RF input. Multiplier 13 multiplies the extracted signal and a carrier-wave signal provided by a local oscillator (RF OSC) 14, to obtain a product, and a low-pass filter (LPF) 15 extracts a low-frequency component from the product, then a base-band received signal on which a quasi-synchronous detection has been performed is provided. The quasi-synchronous detection indicates a detection in which the base-band received signal contains a residual deviation component, because of the fact that there is a deviation between a carrier signal given by the local oscillator 14 and a carrier signal in a received signal. Typically, the local oscillator 14 used in the reception part has an accuracy which can sufficiently be compensated by a signal processing, and the deviation affects to a degree that, in many cases, a quasisynchronous detection signal rotates slowly enough, compared with a symbol interval. In that case, a synchronous detection can be done that detects a phase difference between carrier-wave signals and performs a phase compensation.
In the next stage, gain control is performed on the quasi-synchronous detection signal by an automatic gain controller (AGC) 16, so that an average power of the signal remains constant. Then the signal is converted into a digital signal through an analog to digital (A/D) converter 17. The base-band received signal which has been A/D converted is input to a spread-spectrum IF receiver 18 which acts as a demodulator. The spread-spectrum receiver 18 comprises a demodulator 19, a synchronization acquisition unit (PN Acquisition Loop) 20, a synchronization tracking unit (PN Tracking Loop) 21 and a data decoding unit (Data Decoder) 22. The spread-spectrum communication utilizes pseudo-noise codes which are individually different for each channel in order to isolate and identify a signal from other channel signals. For demodulation of the spread-spectrum signal, it is necessary to multiply pseudo-noise code which is the same as the pseudo-noise code used in a transmitting side and to extract a desired component. Furthermore, the timing of multiplying the pseudo-noise code needs to match that of a received signal.
For that purpose, the spread-spectrum receiver 18 initially acquires a synchronization timing in the synchronization acquisition unit 20 that detects the synchronization timing by changing the phase of the pseudo-noise code. After that, a synchronization tracking unit 21 keeps track of the synchronization timing obtained by the synchronization acquisition unit 20. More specifically, the synchronization tracking unit 21 controls the timing of the pseudo-noise code so that it coincides with the timing of the received signal. This kind of timing tracking is necessary to cope with time-variant fluctuations of a communication path or deviations between transmission and reception of a clock used to generate the pseudo-noise code. The demodulator 19 multiplies the base-band received signal and the pseudo-noise code (which is the same as that used in the transmitting side), in accordance with the timing provided by the synchronization tracking unit 21. The demodulator 19 then integrates the multiplied results over a symbol-duration time. In accordance with the integration result, the symbol is therefore demodulated by a method which corresponds to a respective carrier modulation method. The demodulator 19 also estimates and compensates a transmission and reception carrier-frequency deviation (a phase difference) contained in the base-band received signal. The demodulated symbol is decoded by the data decoder 22 for restoration of transmission information. The restored information is sent out as an output data. This decoding includes frame division, error-correction decoding and voice decoding.
Multiplication of the pseudo-noise code and received signal in the demodulator 19 is called an inverse spread, and calculation extended to include the integration over the symbol-duration time is called a correlation operation. A circuit that executes the correlation operation is referred to as a correlator. In the CDMA method, because a desired signal component is obtained from correlation characteristic of the code, the correlation operation is used not only in the demodulator 19 but in the synchronization acquisition unit 20 and the synchronization tracking unit 21. Accordingly, the correlation operation is a basic operation in a demodulation process of the spread-spectrum signal. Generally, the method of executing this correlation operation is broadly divided into an active correlation method and a passive correlation method. The difference between these two methods depends on their way of giving the pseudo-noise code to be multiplied, that is, one is active while the other is passive.
FIGS. 17 and 18 show conventional arrangements related respectively to an active correlation method and a passive correlation method. FIG. 17 is a block diagram showing a conventional construction of a symbol demodulator comprising sliding correlators, that is, FIG. 17 describes a conventional arrangement of the active correlation method shown in "Digital Communications" by J. G. Proakis, chapter 8 of the second edition, 1989, McGraw Hill Corp. In FIG. 17, the portion surrounded by a dotted line corresponds to a correlating unit (a correlator) 25. In the active correlation method, a base-band received signal (Rx Baseband Signal) and pseudo-noise code generated by a pseudo-noise generator (PN Generator) 26 are multiplied and a correlation operation is executed by integrating the multiplied results over a symbol-duration time (Tb). Thus, the correlator 25 is also called a sliding correlator. Pseudo-noise code to be input to a multiplier 27 is given in time-sequential manner and integration time of an integrator 28 coincides with the symbol-duration time. The integrated symbol is output via a sampler 30 at the timing of a clock from a sample rate clock 31. Generation timing of the pseudo-noise code is controlled by a chip-rate clock 29. Although the circuit configuration shown in FIG. 17 is simple, only one correlation value is provided within each symbol-duration time, that is, the correlation value is output at a symbol interval.
FIG. 18 is a block diagram showing a conventional construction of a symbol demodulation circuit (a matched filter) employing the passive correlation method. The circuit is particularly called a digital matched filter (DMF) if implemented with digital circuitry. In FIG. 18, the portion surrounded by a dotted line corresponds to a correlating unit (a correlator) 35. In the matched filter, a base-band received signal (Rx Baseband Signal) is sampled at a pseudo-noise code rate (i.e. the chip rate) and the sampled signal is input to a shift register 36. The base-band received signals stored in each stage of the shift register 36 are respectively input to multipliers 37, each of which multiplies the base-band received signal and pseudo-noise codes (PN1 to PN7) 38 which are stored in fixed fashion. The result of this multiplication is input to an adder 39 and summed with other multiplied results.
As far as the pseudo-noise code is concerned, it is fixed at least during one data duration time, unlike the case in the active correlation method. As illustrated in FIG. 18, one data is spread by the seven-chip pseudo-noise codes (PN1 to PN7) in the correlation operation. The pseudo-noise code to be multiplied by the first shift-register sample is always the pseudo-noise code PN7 which is the seventh chip. In the configuration using matched filters, one correlation-operation result is output every time a reception sample is input, i.e. at a chip interval. This makes operation speed higher compared with that of a sliding correlator. Therefore, the longer the series length is, the higher the operation efficiency becomes. However, in the above configuration, power dissipation and hardware scale increase, thereby impacting signal quality and system cost. These tendencies are conspicuous when the length of pseudo-noise code for spreading a transmission symbol becomes longer, or a spread efficiency becomes higher.
As explained above, there are primarily two types of correlator for performing correlation operation at the receiving side receiving spread spectrum signals. Either of these types is selected according to circuit scale, power dissipation and operation speed factors. The arrangement of the demodulator 19 for demodulating a symbol as shown in FIG. 16 is the same as shown in FIGS. 17 and 18. In the demodulator 19, the output of the correlator 35 is sampled at the timing when the correlating-operation result is obtained. The synchronization acquiring unit 20 and the synchronization tracking unit 21 execute synchronization acquisition and tracking, respectively, by utilizing the time correlation characteristics of a pseudo-noise code.
The time correlation characteristics of a pseudo-noise code are as follows. The correlation operation produces a higher degree of correlation when the pseudo-noise code timing to be multiplied in the correlation operation coincides with the timing of pseudo-noise code contained in base-band received signal. However, if there is no coincidence between these two timings, the degree of correlation is lower. FIG. 19 indicates the time correlation characteristics of a pseudo-noise code and FIG. 20 shows an enlarged part of such characteristics. In FIGS. 19 and 20, the abscissa is time and the ordinate is a correlation value, and the characteristics show the state when no data modulation is applied. When a symbol modulation is executed by a BPSK modulator, the polarity of a correlation value changes in conformity with the polarity of a transmission symbol.
In FIG. 19, a correlation value exists in the vicinity where a time difference is "0". Needless to say, this characteristic depends on the nature of a pseudo-noise code and a correlation value of small level may exist at positions where a time difference has a value other than "0". Generally, a pseudo-noise code which can be considered to have an average value of "0" is used. In FIG. 19, Tp is the series period of a pseudo-noise code. In a case where a pseudo-noise code having a correlation characteristic shown in FIG. 19 is used, the synchronization acquiring unit 20 performs correlation operation by assuming the timing of a pseudo-noise code. As shown in FIG. 19, if the timing is properly assumed, a higher correlation value is provided. If it is not, no correlation value is provided. Therefore, it is possible to detect a timing in accordance with the magnitude of a correlation value.
FIG. 20 shows an example of correlation characteristic of a pseudo-noise code at a nearby region where a time difference is "0". If the pseudo-noise code is sufficiently random, the correlation characteristic of this region is generally equal to an impulse response given by combined characteristics of a transmission/reception-waveformreshaping filter. That is, when Nyquist transmission is performed for a chip waveform, the impulse response of a Nyquist waveform has a correlation characteristic which is equal to the characteristic at a nearby region where the time difference is "0". Accordingly, as the timing difference increases, the correlation value decreases. When the timing difference is one chip-interval (Tc) apart, the resulting output correlation value is "0". The synchronization tracking unit 21 executes synchronization tracking so that a correlation value for symbol demodulation is maintained at a maximum. In other words, synchronization tracking is performed to make the timing error small.
Configuration of the synchronization acquiring unit 20 will be explained below. A sliding correlator which is based on a conventional synchronization-acquisition method, for example, has a configuration shown in FIG. 21. This method is disclosed in WO96/04716 (PCT/US95/08659) of PCT International Publication. In FIG. 21, the portion surrounded by dotted line is a correlation operation unit 41. This example shows a synchronization acquiring circuit which performs synchronization acquisition for a signal whose transmission symbol is QPSK-spread modulated at the transmission side by using two kinds of pseudo-noise code, i.e., in-phase-axis pseudo-noise code and orthogonal-axis pseudo-noise code. Namely, a base-band transmission signal Tx is given by EQU Tx=d.multidot.(Pi+jPq)
where d is a transmission symbol; Pi, in-phase-axis pseudo-noise code; Pq, orthogonal-axis pseudo-noise code, and j is an imaginary unit. It should be noted that both the transmission symbol and the pseudo-noise code are functions of time, especially, the transmission symbol which is a function of time that changes at every symbol interval and the pseudo-noise code which is a function of time that changes at every chip interval. Details of these functions are omitted here.
A base-band received signal coming through an antenna 42 and a receiver 43 may be expressed as a quasi-synchronization-detection signal Rx as shown below, in the form which contains the phase difference .phi. of the carrier wave. EQU Rx=d.multidot.(Pi+jPq).multidot.exp(j.phi.) EQU =d.multidot.(Pi+jPq).multidot.(cos .phi.+j sin .phi.)
Here, a real component of Rx is an in-phase-axis received signal and an imaginary component is an orthogonal-axis received signal. These components are input to the correlation operation unit 41. In a QPSK despreader 41A, a multiplier and adder/subtractor are configured such that Rx.multidot.(Pi'-jPq') should be obtained, where Pi' and Pq' are codes obtained by assuming the timing of Pi and Pq for the quasi-synchronization-detection signal Rx (these Pi and Pq are both input from a PN generator 44). In digital integrators (Coherent Accumulators) 41B and 41C, the real component and the imaginary component are respectively integrated over the symbol interval, and each integration result is square-summed by a square-sum unit 45, thus outputting correlation power. In other words, if the timing of Pi and Pq and that of Pi' and Pq' match, Pi=Pi' and Pq=Pq' are obtained. Therefore, outputs of the QPSK despreader 41A are the real component and the imaginary component of d.multidot.(cos .phi.+j sin .phi.). If these components are square-summed, d.sup.2 which is a reception symbol power, is provided. Moreover, when there is no match in the above timings, a correlation power having a small level is provided, because the pseudo-noise code is random in nature.
As shown above, because the timing of a pseudo-noise code is unknown at the stage of acquiring synchronization, the timing is assumed at the receiving side, thus providing correlation power associated with a received signal in accordance with the assumed timing. It is determined that the synchronization acquisition of a pseudo-noise code is completed when the power level output exceeds a prescribed level. The reason for using the correlation power for detecting synchronization acquisition is as follows:
(1) it is difficult to grasp a phase .phi. of a carrier wave at the synchronization acquisition stage. PA1 (2) when a signal is data-modulated, modulation data causes the correlation-power amplitude of the received signal to change randomly in polarity at every correlation value, which can be offset by an averaging operation. PA1 a first correlation operation step for performing a correlation operation between the spread code and the base-band component; PA1 a second correlation operation step for performing a correlation operation at a timing equal to a timing difference between the spread code and the base-band component in said first correlation operation step, said timing difference being 1/2 of a spread-code interval; and PA1 an estimation step for estimating, based on results obtained in said first and second correlation operation steps, a correlation operation result at the timing point where a timing difference between the spread code and the base-band component is less than 1/2 of the spread-code interval. PA1 a first correlation operation step for performing a correlation operation on the spread code and the base-band component; PA1 a second correlation operation step for performing a correlation operation on the base-band component and a spread-code which has been offset by 1/2 of a spread-code interval of said spread code; PA1 an estimation step for estimating a correlation operation result at the center point of two timings where said first and second correlation operations have been performed, by adding the results of said first and second correlation steps; PA1 a first weighting step for weighting the result of said first correlation operation step with a first predetermined weight; PA1 a second weighting step for weighting the result of said second correlation operation step with a second predetermined weight; and PA1 a high-accuracy acquiring step for acquiring a highly accurate correlation timing in accordance with results of said estimation step and said first and second weighting steps. PA1 a first correlation operation step for performing a correlation operation on the spread code and the base-band component; PA1 a second correlation operation step for performing a correlation operation on the base-band component and a spread-code which has been offset by 1/2 of a spread-code interval of said spread code; PA1 an estimation step for estimating a correlation operation result at the center point of two timings where said first and second correlation operations have been performed, by adding the results of said first and second correlation steps; PA1 a first weighting step for weighting the result of said first correlation operation step with a first predetermined weight; PA1 a second weighting step for weighting the result of said second correlation operation step with a second predetermined weight; and PA1 an optimum-timing selection step for selecting a correlation operation result or an estimation result at an optimum timing, in accordance with results of said estimation step, and said first and second weighting steps. PA1 a first correlation operation step for performing a correlation operation on the spread code and the base-band component when synchronization acquisition is executed by a correlation operation with a spread code which is assumed to be a base-band component of the received spread-spectrum signal; PA1 a second correlation operation step for performing a correlation operation on the base-band component and a spread-code which has been offset by 1/2 of a spread-code interval of said spread code; PA1 a first power calculation step for calculating correlation power from the result of said first correlation operation step; PA1 a second power calculation step for calculating correlation power from the result of said second correlation operation step; PA1 a first average-correlation-power calculation step for calculating first average correlation power, by performing an averaging operation on the calculation result of said first power calculation step; PA1 a second average-correlation-power calculation step for calculating second average correlation power, by performing an averaging operation on the calculation result of said second power calculation step; PA1 an average-power estimation step for estimating average correlation power at the center point of two timings where said first and second average correlation power have been calculated, by adding the results of said first and second average-correlation-power calculation steps; PA1 a first weighting step for weighting the calculation result of said first average-correlation-power calculation step with a first predetermined weight; PA1 a second weighting step for weighting the calculation result of said second average-correlation-power calculation step with a second predetermined weight; and PA1 a synchronization-acquisition detection step for executing a synchronization-acquisition detection by using the calculation result of said average-power estimation step and weighting results of said first and second weighting steps. PA1 a first code-interval shifting step for shifting a spread code by 1/2 times a code interval when synchronization tracking is executed by a correlation operation with a spread code which is assumed to be a base-band component of the received spread-spectrum signal; PA1 a second code-interval shifting step for shifting a spread code by one code interval when synchronization tracking is executed by a correlation operation with a spread code which is assumed to be a base-band component of the received spread-spectrum signal; PA1 a third code-interval shifting step for shifting a spread code by 3/2 times the code interval when synchronization tracking is executed by a correlation operation with a spread code which is assumed to be a base-band component of the received spread-spectrum signal; PA1 a correlation operation step for performing a correlation operation on the spread code and the base-band component; PA1 a first shift-correlation calculation step for performing a correlation operation on the spread code obtained in said first code-interval shifting step and said base-band component; PA1 a second shift-correlation calculation step for performing a correlation operation on the spread code obtained in said second code-interval shifting step and said base-band component; PA1 a third shift-correlation calculation step for performing a correlation operation on the spread code obtained in said third code-interval shifting step and said base-band component; PA1 a first correlation-power calculation step for calculating a first correlation power from result of said correlation operation step; PA1 a second correlation-power calculation step for calculating a second correlation power from correlation operation result of said first shift-correlation calculation step; PA1 a third correlation-power calculation step for calculating a third correlation power from correlation operation result of said second shift-correlation calculation step; PA1 a fourth correlation-power calculation step for calculating a fourth correlation power from correlation operation result of said third shift-correlation calculation step; PA1 a first average-correlation-power calculation step for calculating an average correlation power by performing an averaging operation on said first correlation power obtained in said first correlation-power calculation step; PA1 a second average-correlation-power calculation step for calculating an average correlation power by performing an averaging operation on said second correlation power obtained in said second correlation-power calculation step; PA1 a third average-correlation-power calculation step for calculating an average correlation power by performing an averaging operation on said third correlation power obtained in said third correlation-power calculation step; PA1 a fourth average-correlation-power calculation step for calculating an average correlation power by performing an averaging operation on said correlation power obtained in said fourth correlation-power calculation step; PA1 a first estimated-average-correlation-power calculating step for estimating an average correlation power at the midpoint of timings where said calculation results have been obtained, by adding calculation results of said first and second average-correlation-power calculation steps; PA1 a second estimated-average-correlation-power calculating step for estimating an average correlation power at the midpoint of timings where said calculation results have been obtained, by adding calculation results of said second and third average-correlation-power calculation steps; PA1 a third estimated-average-correlation-power calculating step for estimating an average correlation power at the midpoint of timings where said calculation results have been obtained, by adding calculation results of said third and fourth average-correlation-power calculation steps; and PA1 a synchronization tracking step for performing synchronization tracking by using calculation results of said first, second, third and fourth average-correlation-power calculation steps and calculation results of said first, second and third estimated-average-correlation-power calculating steps. PA1 spread-code generation means for generating spread codes; PA1 delay means for delaying the spread codes generated by said spread-code generation means and outputting the delayed spread-codes; PA1 first correlation-operation means for performing a correlation operation between said spread codes and said base-band component; PA1 second correlation-operation means for performing a correlation operation between said delayed spread-codes and said base-band component; PA1 timing adjustment means for adjusting output timings of said first and second correlation-operation means; PA1 high-accuracy-timing acquiring means for obtaining correlation-operation result at the midpoint of said output timings, from results of said first and second correlation-operation means whose output timings have been adjusted; and PA1 selection means for outputting a correlation value designated by the correlation-operation result which has acquired the high-accuracy-tining. PA1 spread-code generation means for generating spread codes; PA1 delay means for delaying the spread codes generated by said spread-code generation means and outputting the delayed spread-codes; PA1 first correlation-operation means for performing a correlation operation between said spread codes and said base-band component; PA1 second correlation-operation means for performing a correlation operation between said delayed spread-codes and said base-band component; PA1 square-sum calculation means for calculating respective correlation powers from correlation-operation results of said first and second correlation-operation means; PA1 averaging means for obtaining average correlation power by respectively averaging said respective correlation powers; PA1 high-accuracy-timing acquiring means for estimating average correlation power at the midpoint of timings which correspond to said respectively obtained average correlation power, from said respectively obtained average correlation power; and PA1 a controller for performing a synchronization-acquisition detection by comparing output of said high-accuracy-timing acquiring means and a predetermined threshold level. PA1 serial/parallel conversion means for converting said base-band component, which has been input at a rate twice as high as a chip rate, into first and second parallel output signals having the same rate as the chip rate; PA1 a first matched filter for inputting the first output signal of said serial/parallel conversion means and outputting at said chip rate a correlation value between said base-band component and the first output signal; PA1 a second matched filter for inputting the second output signal of said serial/parallel conversion means and outputting at said chip rate a correlation value between said base-band component and the second output signal; PA1 square-sum calculation means for calculating first and second correlation powers from correlation values of said first and second matched filters, respectively; PA1 averaging means for respectively averaging said first and second correlation powers and outputting first and second averaged correlation powers; PA1 continuous high-accuracy acquiring means for estimating average correlation power at the midpoint of timings which correspond to said first and second averaged correlation powers and time-sequentially outputting the estimated average correlation power; and PA1 reception-path detection means for detecting the timing of a received signal by observing an output level of said continuous high-accuracy acquiring means and performing synchronization acquisition. PA1 spread-code generation means for generating spread codes; PA1 delay means for delaying the spread codes in plural stages; PA1 a plurality of correlation operation means for performing a correlation operation on said base-band component, said generated spread codes and said spread codes delayed in plural stages; PA1 a plurality of square-sum calculation means for calculating respective correlation powers from correlation-operation results of said correlation operation means; PA1 a plurality of averaging means for obtaining average correlation power by respectively averaging said calculated respective correlation powers; PA1 timing adjustment means for adjusting timings for obtaining said plurality of average correlation powers; PA1 first high-accuracy-timing acquiring means for estimating average correlation power at the midpoint of timings which correspond to said average correlation power; PA1 timing control means for performing a timing control based on said estimated average correlation power, by using said plurality of average correlation power whose timings have been adjusted; PA1 clock control means for controlling a spread-code clock in accordance with a control result of said timing control means; and PA1 second high-accuracy-timing acquiring means for selectively outputting the maximum correlation operation result from among a plurality of correlation operation results and estimated correlation-operation values at the midpoint timing, said values having been estimated from said operation results, in accordance with the control result of said timing control means. PA1 pilot spread-code generation means for generating pilot spread codes; PA1 delay means for delaying said pilot spread codes in plural stages; PA1 a plurality of correlation operation means for performing a correlation operation on said base-band component, said pilot spread codes and said spread codes delayed in plural stages; PA1 a plurality of square-sum calculation means for calculating respective correlation power from correlation-operation results of said correlation operation means; PA1 a plurality of averaging means for obtaining average correlation power by respectively averaging said calculated respective correlation powers; PA1 timing adjustment means for adjusting timings for obtaining said plurality of average correlation powers; PA1 first high-accuracy-timing acquiring means for estimating average correlation power at the midpoint of timings which correspond to said average correlation power; PA1 timing control means for performing a timing control based on said estimated average correlation power, by using said plurality of average correlation power whose timings have been adjusted; PA1 clock control means for controlling a spread-code clock in accordance with control result of said timing control means; PA1 second high-accuracy-timing acquiring means for selectively outputting a maximum correlation operation result from among a plurality of correlation operation results and estimated correlation-operation values at the midpoint timing, said values have been estimated from said operation results, in accordance with the control result of said timing control means; and PA1 synchronization detection means for performing a channel estimation and a phase compensation by using outputs from said second high-accuracy-timing acquiring means. PA1 spread-code generation means for generating spread codes; PA1 delay means for delaying the spread codes in plural stages; PA1 a plurality of correlation operation means for performing a correlation operation on said base-band component, said generated spread codes and said spread codes delayed in plural stages; PA1 a plurality of delay means for respectively delaying said plurality of correlation-operation results by the time required for a channel estimation; PA1 a plurality of synchronization detection means for respectively performing a phase compensation and a weighting by using values associated with said channel estimation; PA1 a plurality of inverse modulation means for respectively performing an inverse modulation by using data which has temporarily been judged for said synchronization detection means; PA1 averaging means for performing an averaging operation on said plurality of inverse-modulated results; PA1 first high-accuracy-timing acquiring means for estimating average correlation-operation result at the midpoint of timings which correspond to said average correlation-operation results, by using said plurality of average correlation-operation results whose timings have been adjusted; PA1 timing control means for performing a timing control based on said estimated average correlation-operation result; PA1 clock control means for controlling a spread-code clock in accordance with the control result of said timing control means; PA1 second high-accuracy-timing acquiring means for selectively outputting the maximum correlation operation result from among a plurality of correlation operation results and estimated correlation-operation values at the midpoint timing, said values have been estimated from said operation results, in accordance with the control result of said timing control means; PA1 channel estimation means for estimating a channel by using correlation-operation results given by said second high-accuracy-timing acquiring means; and PA1 third high-accuracy-timing acquiring means for selectively outputting synchronization-detection result by which a maximum synchronization detection level is obtained, from among a plurality of synchronization-detection results and estimated synchronization detection values at the midpoint timing, said values have been estimated from said synchronization-detection results, in accordance with the control result of said timing control means. PA1 serial/parallel conversion means for converting said base-band component, which has been input at a rate twice as high as a chip rate, into first and second parallel output signals having the same rate as the chip rate; PA1 a first matched filter for inputting the first output signal of said serial/parallel conversion means and outputting at said chip rate a correlation value between said base-band component and the first output signal; PA1 a second matched filter for inputting the second output signal of said serial/parallel conversion means and outputting at said chip rate a correlation value between said base-band component and the second output signal; PA1 square-sum calculation means for calculating first and second correlation powers from correlation values of said first and second matched filters, respectively; PA1 averaging means for averaging said first and second correlation powers and outputting first and second averaged correlation power, respectively; PA1 first continuous high-accuracy acquiring means for estimating average correlation power at the midpoint of timings which correspond to said first and second averaged correlation powers and time-sequentially outputting the estimated average correlation power; PA1 phase compensation means for phase-compensating outputs of said first and second matched filters; PA1 second continuous high-accuracy acquiring means for estimating a synchronization-detection signal at the midpoint of timings from said phase-compensat ed synchronization-detection signals and time-sequentially outputting the estimated synchronization-detection signals; and PA1 RAKE synthesizing means for multiplying and synthesizing outputs of said first continuous high-accuracy acquiring means weighted by the average correlation power and outputs of said second continuous high-accuracy acquiring means.
Generally, in order to reduce effect of noise, the correlation powers obtained at the same timings are, in many cases, averaged and the average correlation power is used to determine the completion of synchronization acquisition. In FIG. 21, an averaging unit (Non-Coherent Accumulator) 46 integrates correlation power which is obtained at every symbol interval, for a predetermined duration of time (i.e., a predetermined number of times) so as to average the power, and thereby reduce the effect of noise. After that, a comparator (Threshold Comparator) 47 compares the average power with a threshold level and sends the result to a control unit (Search Controller) 48 to determine synchronization-acquisition detection. If it is determined that the synchronization acquisition has been achieved, synchronization tracking and symbol demodulation are performed. If, on the other hand, the synchronization acquisition is incomplete, another timing different from the previous one is assumed and the operations mentioned above are repeated.
Though the method using a sliding correlator requires a simply-configured circuit, only one correlation value is provided at each symbol-interval. This requires an unacceptably long time for acquiring synchronization. To avoid this, some measures are taken such as implementing a synchronization-acquisition circuit which has a several systems for shortening the synchronization-acquisition time. For example, by setting the number of integrations for averaging and using plural threshold levels, primary evaluation may be accomplished based on a short integration time and a low threshold level, and secondary evaluation may be executed based on a longer integration time, only in a case where there is a high possibility that the reception timing matches.
If the reception timing is changed at a chip interval, only a correlation value having an accuracy related to the chip interval is provided. As understood from the characteristic shown in FIG. 20, when an appropriate reception timing is, for example, (n+0.5) chip, only the correlation power conforming to a correlation value obtained at the timing which is shifted 0.5 chip ([1/2] Tc) away from the proper timing, is provided at chip phases n and n+1. This causes degradation of acquisition performance. That is, even when the timing is close to the appropriate timing, a low correlation value makes timing detection difficult. To cope with this problem, detection of synchronization acquisition is executed, in most cases, by changing the reception timing with an accuracy of 0.5 chip-interval, that is, by changing the assumed timing by a step of 0.5 chip-interval.
A synchronization-acquiring circuit related, for example, to a digital matched filter is shown in FIG. 22. The configuration shown in FIG. 22 is disclosed in Journal of Institution of Electronics and Communications Engineers, Vol. 69-b, No. 11, pp. 1540-1547, entitled "Spread-spectrum communications apparatus for satellite communication, which directly performs data demodulation by a matched filter", by Hamamoto et al. Each output of the digital matched filter, which will give the correlation-operation result for the in-phase-axis signal and the orthogonal-axis signal, is squared by squarers 50A and 50B, respectively. The result is then summed by an adder 51, thus providing the correlation power.
The synchronization-acquiring unit shown in FIG. 21 outputs the correlation power at every symbol interval, while, the synchronization-acquiring circuit shown in FIG. 22 outputs the correlation power at [1/2] chip-interval. (Note that the method of giving two of the power, instead of one, at every chip-interval will be described later.) For example, if the period of the pseudo-noise code matches the symbol-duration time, the correlation power can be obtained with a resolution of [1/2] chip-interval in the synchronization-acquiring unit, by observing square-sums of the symbol-interval as shown in FIG. 21.
In the synchronization-acquiring unit shown in FIG. 22, a recursive integrator 52 executes an averaging operation using recursive addition, which will reduce the effect of noise. The recursive integrator 52 comprises an adder 52A to which the square-sums are input, a frame memory 52B for storing one pseudo-noise frame and a multiplier 52C which multiplies the output of the frame memory 52B by a predetermined coefficient.
The recursive addition is realized by feeding the output of the multiplier 52C to the adder 52A. By storing in the frame memory the result of the recursive addition that is performed in a symbol-period unit on the correlation power provided at every [1/2] chip-interval, the averaging operation may be executed without confusing the correlation power between different code-phase timings. The point in the frame memory 52B, at which the maximum averaged-correlation power is provided, is held by a maximum-value hold unit 53 and this point will be considered as the reception timing.
Similar to the sliding correlator and for the purpose of preventing degradation of the synchronization-acquiring performance caused by a correlation-value test with a chip-interval accuracy, the configuration shown in FIG. 23 may be adopted as the digital matched filter in the circuit shown in FIG. 22. In FIG. 23, the same references are used as in FIG. 18 to denote the corresponding parts and references with a suffix A denoting similar parts.
In FIG. 23, the portion surrounded by a dotted line corresponds to a correlating unit 35A. The input to a digital matched filter is sampled at a rate twice as high as that of PN clock; that is, it is over-sampled by two at each chip. Correspondence is then made between the PN code 38 to be multiplied by an input signal and the successive two samples for one chip. In this way, one sample of a correlation value is output at every [1/2] chip, thus preventing degradation of synchronization-acquiring accuracy.
FIGS. 24A and 24B show the results of correlation performed by the unit shown in FIG. 23. FIG. 24A depicts the result of an ordinary correlation operation. Assuming that S.sub.0 is the correlation-operation result at the most suitable sampling timing, correlation-operation results S.sub.-1 and S.sub.1 at sampling timings adjacent to the timing of S.sub.0, are small compared with S.sub.0. In the configuration shown in FIG. 23, since a reception sample is input at a rate twice as high as the chip rate, the correlation-operation result is also obtained twice as fast as the chip rate. However, the pseudo-noise code whose sign bit is the same over two samples is multiplied and then summed together, therefore, as shown in FIG. 24B, the result of correlation operation executed twice as fast as the chip rate shows a value which is equal to that obtained by adding adjacent samples together. It should be noted that FIG. 24B shows the case in which the obtained result is divided by 2 and averaged. In other words, the maximum correlation value A.sub.0 is a value obtained by adding correlation values S.sub.0 and S.sub.1, where S.sub.0 is a sample input [1/4] Tc prior to the synchronization timing and S.sub.1 is a sample input [1/4] Tc after that timing.
The theoretical analysis of such a method, including the effect of a transmission/reception-waveform reshaping filter is disclosed in "Performance of Soft Decision Digital Matched Filter in Direct-Sequence Spread-Spectrum Communication Systems" by Kataoka et al., IEICE Transactions, Vol. E74, No. 5, pp. 1115-1122, May 1991. According to this paper, degradation occurs at the most suitable sampling point in view of the signal to noise ratio, however, the degree of the degradation is very slight (0.06 dB in case of a root Nyquist filter having 40% of a transmission/reception equally-divided roll-off rate). According to this theoretical analysis, it can be recognized that at a portion where a timing error is large (approximately [1/2] Tc), the amount of degradation of the signal to noise ratio caused by the timing error is negligible.
The configuration of a conventional synchronization-tracking unit will be explained below. The synchronization-tracking unit basically comprises an element called a delay locked loop (DLL). FIGS. 25 and 26 show a conventional delay locked loop comprising a sliding correlator. FIG. 25 indicates configuration called an asynchronous DLL, while FIG. 26 depicts configuration called an inverse-modulation-type synchronous DLL. In FIGS. 25 and 26, portions surrounded by dotted lines are correlating units 58, 59, 70, 71 and 72.
The asynchronous DLL shown in FIG. 25 is disclosed in "A Digital Chip Timing Recovery Loop for Band-Limited Direct-Sequence Spread-Spectrum Signals" by R. D. Gaudenzi, IEEE Transactions on Communications, Vol. 41, No. 11, pp. 1760-1769, Nov. 1993. In FIG. 25, a complex base-band received signal (an in-phase-axis received signal and an orthogonal-axis received signal) is reshaped in waveform by a low-pass filter (LPF) 55, and sampled by a sampler 56 at an oversampled-by-two rate per chip. The result is fed into a serial/parallel converter (S/P) 57.
The output of the S/P 57 is divided into the following samples: a sample O (On Timing) used for symbol demodulation and samples E and L (Early and Late Timings) used for detection of a timing error for a synchronization tracking. In other words, a base-band received signal which is shifted in [1/2] chip-interval from the symbol demodulation timing, is used for detecting the timing error.
In FIG. 25, sample E (one of the input samples to a timing-tracking system) is directly subjected to a correlation operation by a multiplier 59A, while another sample, sample L, is subjected to a correlation operation by a multiplier 58B after it is delayed by a delay 58A by the amount of one chip. Hb(z)'s are low-pass filters corresponding to digital integrators. These correlation-operation results passing through the two systems are respectively squared by squarers 60A and 60B for removing effects of a carrier-wave phase, a symbol modulation, etc. and thereby changed to correlation power. An error signal is then generated by calculating a difference of the correlation powers with a subtracter 61. The error signal is input into a numerical control clock (NCC) 62. In the NCC 62, an averaging operation is performed on the error signal to reduce the effects of noise components and the like, then a sample clock of a received signal is controlled so that the error signal is reduced to 0.
FIGS. 27A and 27B show a correlation-power characteristic and an error characteristic, respectively. In FIG. 27A, the ordinate is correlation power and the abscissa is a time difference. This characteristic is called an autocorrelation characteristic of a spread-spectrum signal. It shows a typical curve of the characteristic, as shown in FIG. 20. If the effect of noise is small enough, the correlation power of a symbol has a maximum value, provided that the symbol is sampled at an appropriate timing (a time difference is 0). Furthermore, the correlation power will be reduced as the time difference becomes large.
In FIG. 25, a timing for the sample E is set [1/2] chip-interval earlier than that for the sample O which is used for a symbol demodulation. Accordingly, the sample E and the sample L whose sampling time is delayed one chip-interval from the timing of the sample E, exhibit the correlation power as shown in FIG. 27A. In this case, if the timing of the sample O is ideal, the correlation characteristic becomes symmetrical. This makes the correlation power of the samples E and L equal and an error signal becomes 0. If the timing of the sample O lags a little behind the appropriate timing, the correlation power of the sample E is greater than that of the sample L. As a result, the error signal becomes negative in value.
FIG. 27B shows a relationship between the error signal and a timing shift from an appropriate timing, with respect to the sample O. In FIG. 27B, the abscissa is a time difference and the ordinate is the error signal. That is, FIG. 27B shows that if the error signal is negative, the timing lags, however, if it is positive, the timing leads.
The configuration shown in FIG. 25 requires a squaring operation after the correlation operation in order to use a symbol modulation signal. However, it is not necessary to implement squarers 60A and 60B if, for example, a synchronous detection is ideal and the error signal is generated from a pilot signal and the like on which no symbol modulation is executed. In that case, the squarers 60A and 60B in FIG. 25 are omitted, and the configuration without these squarers is called a synchronous DLL. Therefore, enhancement of synchronization-tracking performance can be expected. Even in a case where a symbol-modulated spread-spectrum signal is used, an ideal synchronous detection realizes a DLL of a synchronous type by returning the polarity of the symbol modulation to the original one. The DLL configuration owing to such operation is called an inverse-modulation-type synchronous DLL.
FIG. 26 shows a conventional configuration of DLL called an inverse-modulation-type synchronous DLL, which is the configuration disclosed by Sawahashi et al., in The Technical Report of Institution of Electronics, Information and Communications Engineers, RCS94-50, pp. 13-18, Febuary 1995, entitled "An inverse-modulation-type coherent DLL in DS-CDMA". In FIG. 26, the portions surrounded by a dotted line are correlating units 70, 71 and 72; the portion surrounded by alternate long and short dash line is a synchronization-tracking unit 68; and the portion surrounded by alternate long and two short dashes line is a symbol-demodulati on unit 69.
The voltage-controlled pseudo-noise code generator (VCCG) 78 that is included in a correlator is a pseudo-noise generator whose generation timing is controlled by a voltage controlled signal, that is, an error signal. While the DILL shown in FIG. 25 executes synchronization tracking by controlling the sampling timing of an input sample, the DLL shown in FIG. 26 does the synchronization tracking by controlling the generation timing of the spread-spectrum code.
As far as the timing control is concerned, the configuration shown in FIG. 25 and that in FIG. 26 provide a similar performance, provided that the relative timing relationship between a received signal and a pseudo-noise code is controlled. The performance does not depend upon the difference between an asynchronous DLL and an inverse-modulation-type synchronous DLL. It is advantageous to adopt a method of controlling the generation timing of the pseudo-noise code when a RAKE receiver (which will be mentioned later) shares an analog-to-digital converter, independently performs synchronization tracking of the timing of the reception-path signal and executes demodulation. Note that when a DMF (which will be also mentioned later) is used, a method of controlling an input-sample timing is adopted so that a timing of peak value, for example, comes to the center position, because the code phase is fixed.
In FIG. 26, after a quasi-synchronous detection is performed on a received signal (a spread signal) in a QPSK quasi-synchronous detector (Quasi-quadrature Detector) 65, the signal is sampled by a sampler 67 at a rate which is integral multiples of a chip-interval, and the sampled signals are input into a symbol demodulator 69 and a synchronization-tracking unit 68, respectively. The symbol demodulator 69 performs a correlation operation with a pseudo-noise code which has a timing synchronized with the received signal. It should be noted that there remains the effect of a carrier-wave phase-difference .phi. in the quasi-synchronous detection signal. Assuming that a symbol is d, this effect is expressed by d.multidot.exp(j.phi.). .phi. is estimated in a carrier-wave phase estimation unit (Carrier Phase Estimator) 79 and exp(-j.phi.') is generated from the estimation result .phi.'. The product of the generated result and the correlation-operation result is then used for a symbol demodulation.
The synchronization-tracking unit 68 performs a correlation operation between a pseudo-noise code with a timing which is leading a symbol timing and a pseudo-noise code which is lagging behind the symbol timing, and provides a difference between the two operation results. Other than error signal component, the correlation-operation result includes effects of a modulation symbol d and a carrier-wave phase difference .phi.. These effects can be described as .epsilon..multidot.d.multidot.cos(.phi.), where .epsilon. is an error signal.
The modulation symbol d and the carrier-wave phase difference .phi. are removed by using d' estimated in the symbol demodulator (Data Decision) 81 and a phase difference .phi.' estimated in the carrier-wave phase estimation device 79, thus providing an error signal .epsilon.'. The operation for removing the effect of d by using d' is an inverse modulation. .epsilon.' is input into a loop filter 76 and averaged to reduce effects of noise. After that, the averaged .epsilon.' is input into a voltage-controlled pseudo-noise code generator (VCCG) 78 as .epsilon., so as to control its timing. In this way, with the adoption of the inverse modulation, a square-sum circuit for removing effects of the carrier-wave phase difference and the modulation symbol is not required. This brings about no multiplying loss (Squaring Loss), therefore, it is possible to reduce the effects of noise components and furthermore, to improve performance of the synchronization tracking.
FIG. 28 shows an example of a timing-tracking unit using a digital matched filter. Configuration of this filter was presented by Kataoka et al. as "A digital synchronization method for use in a spread-spectrum communication, using a soft decision matched filter" in The Technical Report of Institution of Electronics, Information and Communications Engineers, RCSS91-4, pp. 23-30, May 1991. In the part shown in FIG. 28, outputs of two low-pass filters (LPFs) 87A and 87B, which are a quasi-synchronous detection signal, are A/D converted by A/D) converters 88A and 88B at a rate twice as high as the chip rate, and the converted signals are input into digital correlators 89A and 89B by the same clock.
The basic configuration of the digital correlator of FIG. 28 is the same as that of FIG. 23. The digital correlators 89A and 89B output the correlation-operation result at an interval twice as fast as the chip-interval. Outputs of the two correlators 89A, 89B are fetched at a symbol timing, and a reception symbol is demodulated if a phase compensation is executed. Then, effects of a carrier-wave phase and a modulation symbol are removed from outputs of the two correlators by squaring circuits 90A and 90B and an adder 91. Thus, the correlation power is provided. The correlation power is then divided into two parts, one of them is delayed by a delay circuit 92 having one chip interval. After that, a difference between the delayed power and the correlation power which has by-passed the delay circuit 92 is calculated by a subtracter 93. The subtracter outputs an error signal. When the digital matched filter shown in FIG. 28 is used, a subtracter output which has a timing containing a significant error signal (a symbol timing), is extracted by a latch circuit 94.
The error signal is averaged by a loop filter 95 to reduce effects of noise and this signal is input into a voltage-controlled oscillator (VCO) 96, so that a reception timing of a quasi-synchronous detection signal is controlled. Note that the relationship between the symbol timing of a correlation value and the timing which gives an error signal is similar to that described in FIGS. 25 and 27. That is, the timing when the error signal is latched corresponds to the next sample of a symbol timing (1/2 chip-interval later).
In the example shown in FIG. 28, the voltage-controlled oscillator (VCO) 96 comprises analog circuits and output of the VCO 96 is A/D converted. However, in view of miniaturization of an apparatus and its productivity, the VCO is preferably composed of digital circuits. In this case, it is conceivable that the apparatus has a configuration in which clock control is performed in a digital manner, similar to the configuration shown in FIG. 25.
FIG. 29 shows a conventional digitally-controlled clock generator presented by Takakusaki et al., entitled "Development of a digital-controlled clock generator for use in DLL", at the conference of communication society of the Institution of Electronics, Information and Communications Engineers, B-371, March 1996. A typical voltage-controlled oscillator (VCO) directly changes output frequencies by using an analog-controlled voltage. The generator shown in FIG. 29 directly changes the phase of an output clock by a digitally-controlled signal 98, with arrangement of a fixed clock 97 faster than the chip rate. In other words, the generator employs a method in which the delay time of a programmable delay element 99 is changed in accordance with a control value of the digitally-controlled signal 98, thus changing the phase of the clock. Through a divider circuit, clock control is performed in a digital manner on an output signal whose delay time has been controlled. In this case, because the units that update the timing are discrete, it is necessary to provide a clock as a basic clock which is faster than the chip rate, so as to realize a synchronization-tracking characteristic with higher accuracy. For example, if the fixed clock 97 is n times faster than the chip rate, the unit of controlling the chip timing is a 1/n chip-interval.
The chip rate is considerably higher than the symbol rate and is usually designed to have a spread rate ranging from a few 10 times to a few 100 times higher than the symbol rate, which requires a high-speed operation. Furthermore, it is required that the control unit of FIG. 28 operate at a rate n times higher than the chip rate, so as to realize a synchronization-tracking characteristic with high accuracy. Power dissipation of a digital circuit greatly depends on operation speed. Accordingly, a digital synchronization-tracking unit has a problem to solve such that an operation rate should be reduced without deteriorating the synchronization-tracking characteristic.
FIG. 30 shows another example of a conventional digitally-controlled clock generator. The concept of this generator is disclosed in "Phase Noise and Transient Times for a Binary Quantized Digital Phase-Locked Loop in White Gaussian Noise" by Cessna et al., IEEE Transaction on Communication, COM-20, No. 2, pp. 94, 1972. In FIG. 30, the timing of a free-running clock 100 which has a rate of chip-interval multiplied by integer, is controlled by a timing control signal in a pulse insertion/decimation circuit 101. To increase the timing, pulses are inserted into the clock signal. Digital circuits, for example, operate at a rising edge of the pulse; therefore, when pulses are inserted, the timing relatively leads. To lag the timing, clock pulses of a clock signal are decimated. If the free-running clock 100 has a rate n times higher than the chip rate, the timing controlled by insertion/decimation of one pulse is equal to [1/n] chip-interval.
In a circuit shown in FIG. 30 which is small in circuit scale compared with that of FIG. 29, the pulse-insertion operation needs to be faster than the free-running clock. Accordingly, in view of lowering power dissipation, a digital synchronization-tracking unit also has a problem to solve that operation speed should be reduced without deteriorating the synchronization-tracking characteristic.
In mobile communications, multi-path fading exerts a negative influence. As a result, a received signal comprises a multiple of reception-path signals having different timings, which vary their carrier-wave phase and magnitude independently. Because a spread-spectrum signal makes use of time-correlation characteristic caused by pseudo-noise code, the reception-path signals can be received separately and discriminately if the arrival-time difference of the reception-path signals is more than one chip-interval. Furthermore, reception characteristic can be improved by combining the separately-discriminated reception-path signals. Such a reception method is referred to as a RAKE reception.
FIG. 31 illustrates construction of a conventional RAKE receiver which is disclosed in U.S. Pat. No. 5,490,165. The RAKE receiver shown in FIG. 31 comprises a searcher element 105, a plurality of demodulation elements 106, a symbol combiner 107 and a controller 108. The searcher element 105 searches for a transmission signal from peripheral base stations and time-variant reception conditions such as timing and signal power of received multi-path signals. The demodulation elements 106 perform a synchronization tracking and, at the same time, perform symbol demodulation on each of the reception-path signals. The symbol combiner 107 combines symbol demodulation results of each of the demodulation elements 106. The controller 108 controls allocation of the reception-path signals which the demodulation elements 106 should demodulate, in accordance with searching result of the searcher element 105, result of the synchronization tracking and the demodulation symbol power of the demodulation elements.
In FIG. 31, a signal search executed by the searcher element 105 is a synchronization-tracking-like operation, and is realized by the configuration shown in FIG. 21, with respect to an apparatus construction. It should be noted that the configuration of FIG. 31 is slightly different from that of FIG. 21 in that the configuration of FIG. 31 executes a search for the reception-path signals while doing the synchronization tracking and the symbol demodulation. That is, there is a need to search for a new reception-path signal and re-allocate it to the demodulation elements 106 so as to avoid a complete step out, before all of the signals associated with synchronization tracking and symbol demodulation by the demodulation elements 106 become unable to be demodulated due to fluctuation of level caused by multi-path fading.
Therefore, it is necessary for the searcher element 105 to search for signals in a short period of time and with high accuracy. In particular, in order for the demodulation elements 106 to operate shortly after allocating a reception-path signal to the demodulation elements 106, the synchronization time needs to be shortened. At the time of a synchronization acquisition, accuracy in time is required. In such a case, a sliding correlator may have a lot of correlators connected in parallel to measure correlation power simultaneously, though at different timings. However, this raises a problem that as the number of correlators connected in parallel increases, the resulting hardware increases in both cost and size.
FIG. 32 shows in detail an arrangement of the demodulation elements 106 of FIG. 31, which is disclosed in U.S. Pat. No. 5,490,165. In FIG. 32, the portion surrounded by a dotted line is a correlating unit 110. Filters 110B and 110C extract a non-modulated pilot signal contained respectively in an in-phase-axis reception signal and an orthogonal-axis reception signal and then average those signals. Only spread modulation is performed on this pilot signal. The conventional arrangement shown in FIG. 32 illustrates a RAKE receiver for the pilot signal on which the information signal is code-division multiplexed at a transmission side. The non-modulated pilot signal and the information signal are code-division multiplexed by an orthogonal code (Walsh Function). That is to say, since the pilot signal and the information signal are multiplexed by the codes which are orthogonal to each other, the pilot signal is separated from the information signal only by performing integration as follows.
Outputs from a QPSK despreader 110A and from an orthogonal-code generator (Walsh Function Generator) 111 are multiplied by multipliers 110D and 110E. The multiplied results are output through accumulators 110F and 110G. This enables channel estimation. To realize a RAKE reception with a maximum-ratio compound, a weighting phase-compensation unit (Data Scale Phase Rotation) 112 estimates the phase difference of a carrier wave and amplitude of a received signal. It also implements a phase compensation and, at the same time, performs a weighting by the estimated amplitude, thus outputting a weighted synchronization-detection symbol. The symbol is input into a symbol storage register (FIFO) 113 and the timing is adjusted so that the symbol is output to a symbol combiner 107 (FIG. 31) at the same timing as other reception-path signals.
The following is a quantitative explanation. Assuming that, in descending order of reception timings, three reception-path signals have reception amplitudes, .rho..sub.0, .rho..sub.1, .rho..sub.2 ; carrier-wave phases, .phi..sub.0, .phi..sub.1, .phi..sub.2 ; and delay times, 0, t.sub.1, t.sub.2 indicating a delay time from the fastest reception timing, a base-band reception signal MRx is expressed as follows. EQU MRx=.rho..sub.0 .multidot.d(t).multidot.exp(j.phi..sub.0)+.rho..sub.1 .multidot.d(t+t.sub.1).multidot.exp(j.phi..sub.1)+.rho..sub.2 .multidot.d(t+t.sub.2).multidot.exp(j.phi..sub.2)
Output of each demodulation element 106 (FIG. 31), which has been phase compensated and weighted, is .rho..sub.0.sup.2 .multidot.d(t), .rho..sub.1.sup.2 .multidot.d(t+t.sub.1) and .rho..sub.2.sup.2 .multidot.d(t+t.sub.2), respectively. When storage time of a symbol storage register 113 is respectively set to .tau..sub.0, .tau..sub.0 -t.sub.1 and .tau..sub.0 -t.sub.2 (.tau..sub.0 .gtoreq.t.sub.2), output of the demodulation element 106 is .rho..sub.0.sup.2 .multidot.d(t+.tau..sub.0), .rho..sub.1.sup.2 .multidot.d(t+.tau..sub.0) and .rho..sub.2.sup.2 .multidot.d(t+.tau..sub.0), respectively. If these outputs are combined by the symbol combiner 107 (FIG. 31), a symbol weighted with the power (.rho..sup.2) is obtained.
The synchronization tracking unit shown in FIG. 32 also has a DLL configuration. That is, after a timing adjusting unit (Time Skew) 115 adjusts the timing of a pseudo-noise code given by a pilot pseudo-noise code generator (Pilot PN Generator) 114 so as to obtain an error signal, a correlator 116 comprising a QPSK despreader 116A and an integrator 116B performs a correlation operation. This correlation operation results in producing the error signal. A timing controller (Time Tracking) 117 averages the error signal to mitigate effects of noise, then the synchronization tracking unit executes a synchronization tracking so that the demodulation timing becomes appropriate.
In order to obtain prescribed timing accuracy similar to that obtained in the timing controller shown in FIG. 29 or FIG. 30, it is necessary for the timing controller 117 to operate at a higher rate which exceeds the chip rate. There is also a need for the timing controller 117 to operate so as to make power dissipation as low as possible, without deteriorating the accuracy. Furthermore, since the RAKE receiver of FIG. 31 has a plurality of demodulation elements 106, each of which contains a timing controller that requires a high-speed operation, low power dissipation is particularly a major subject for the RAKE receiver. In FIG. 32, the timing adjusting unit 113 for combining a symbol has an FIFO configuration, which raises a problem that the scale of the FIFO and its power dissipation become large as the operation speed becomes higher.
FIG. 33 shows configuration of a RAKE receiver using digital matched filters in the multi-path fading environment. This is a construction reported by G. L. TURIN in PROCEEDING OF THE IEEE, Vol. 68, No. 3, March 1980, entitled "Introduction to Spread-Spectrum Antimultipath Techniques and Their Application to Urban Digital Radio". In the receiver, an output signal of correlator on which synchronous detection has been performed is input into a delay circuit (Delay Line) 118, in which a timing adjustment is performed on multi-path received signals so that their combined timings coincide. The timing-adjusted signals are subjected to a weighting which corresponds to a reception amplitude of the multi-path received signals, then these signals are added in an addition unit (Summing Bus) 119. It is possible to prevent intrusion of unrequited noise by making the weighting 0 which corresponds to the timing when no multi-path signal is detected.
In the example shown in FIG. 33, an input signal to the RAKE receiver is a synchronous detection signal. However, it may have a configuration such that a correlation-operation output in which a carrier-wave phase difference remains is input, and at the same time a phase compensation is performed at a portion where the weighting is applied. For the weighting and the phase compensation, estimation of a reception amplitude .rho. and a carrier-wave phase .phi. is accomplished in a similar manner as shown in FIG. 26 or in FIG. 32.
In a case where the digital matched filter is used, a correlation value or correlation power is given at every interval of providing an input sample to the digital matched filter, i.e., at a rate faster than the chip rate. This makes synchronization acquisition and synchronization tracking relatively easy, however, only a correlation value associated with the time difference of equal interval can be detected. When raising the timing accuracy, it can be considered to expand the construction of FIG. 23 to that of FIG. 34 (in which the same numerals are used as in FIG. 23 to denote the same parts, while numerals with a different suffix denote similar parts). However, because a high accuracy requires expanding the circuit scale and increasing power dissipation, the construction becomes difficult and costly. Accordingly, an input-sample rate is limited by itself and it is also difficult to acquire a high-accuracy timing. This results in a continuing problem in that a timing error lowers signal power.
By taking the above problem into consideration, there reported construction as shown in FIG. 35, which is disclosed in Japanese laid-open publication No. 7-95125. In this publication, n digital matched filters 121 are arranged in parallel to realize low power dissipation. This construction is similar to a construction in which sliding correlators are operated in parallel, and reduces an operation speed by the number of parallel-arranged filters. In FIG. 35, a plurality of digital matched filters 121 are provided, which operate by a clock 122 same as the chip clock, though different in phase to each other. These filters respectively output a correlation value or correlation power to a multiplexer 123, and the multiplexer 123 outputs the value in a series manner. In this way, a high timing accuracy is obtained, while an operation speed of the digital matched filters 121 is kept to the chip rate.
However, an increase in a hardware scale due to parallel arrangement of the digital matched filters 121 is enormously large and the parallel arrangement also increases the amount of power dissipation, in spite of the fact that the maximum operation speed can be kept low. Accordingly, there still remains a problem that both hardware scale and power dissipation are unacceptably large.